The most common prior art frequency doubler is shown in FIG. 1A. In the circuit shown in FIG. 1A, the input signal In is delayed through delay device 20, and then the delayed signal XORs with the original input signal at XOR gate 22. The circuit in FIG. 1A is essentially an edge detector. FIG. 1B shows a plot the input signal In, delayed signal InD, and output signal Out for the circuit of FIG. 1A. The problem of this circuit is that it requires a 50% duty cycle of the input signal. If the input signal does not have 50% duty cycle, the output frequency will not be stable as shown in FIG. 1B. The other problem is that the duty cycle of the output signal varies with input signal frequency, temperature, process and other variables due to the fixed RC delay element.
The output of the XOR gate in FIG. 1 is fed to a RC low pass filter. The DC component of the low pass filter is compared to a reference voltage V, usually a half value of power supply voltage, for 50% duty cycle. The feedback circuitry 24 shown in the prior art circuit of FIG. 2A solves the fixed delay problem of the prior art circuit in FIG. 1A. A plot of the input signal In, input delay signal InD, and output signal Out for the circuit of FIG. 2A is shown in FIG. 2B. However, this circuit still exhibits two main problems. First, it employs a low pass filter consisting of a large resistor R and capacitor C to have lower conner frequency. Because of the RC time constant, the response time of the circuit of FIG. 2A is also very long. The second problem is the same as in the prior art circuit of FIG. 1A. It still requires a 50% duty cycle of the input signal In, otherwise the output frequency will not be stable.
In another prior art circuit, the frequency doubler circuit receives four input signals in quadrature and combines them to produce a pair of antiphase signals at twice the input frequency. The circuit requires four quadrature inputs which are usually not available.
Another prior art circuit receives an input signal having a first frequency which is input to a phase shifting circuit element to provide an intermediate signal resembling the input signal except shifted in phase. The intermediate signal is provided to a logic element which combines the intermediate frequency with the input signal to produce an output signal having a second frequency which is double the first frequency. The drawback is that it requires the input signal have exactly 50% duty cycle, otherwise it will not only have the same issue as described above, but also the integrator in the circuit will saturate and make the doubler fail.